Advanced System-Level Verification for Next-Generation Processor Cores
June 18, 2026Breker Verification Systems Engineering, 2025–26
Liaison(s): Adnan Hamid, Leigh Brady, Brian Barker, Arun Rajeev, Scott Biggio
Advisor(s): David Harris
Students(s): Jordan Carlin (TL-F), Marina Bellido (TL-S), Massin Ihs (S), Huanhuan Huang (S), Eoin O’Connell (S), Gabe Alencar (S), Cheyenne Trujillo (F), Tian Xie (F), Connor Jones (F)
Breker Verification Systems is an electronic design automation company focused on RISC-V processor verification. The Clinic team has extended Breker’s test suite to support three new RISC-V features: PMP, Sdtrig and External Debug. For each feature, the team developed comprehensive test plans based on the RISC-V specification and implemented C++ graph-based models to generate tests accordingly. These deliverables enhance Breker’s verification suite for next-generation processor cores.