MicroWorkshop | Big Problems in Circuit Design – July 22, 2020
Speakers
Hahn-Phuc Le | Integrated Power Delivery for High-Performance Computing
Hahn-Phuc Le | Integrated Power Delivery for High-Performance ComputingProject Abstract
The integrated Power Electronics and Energy-Efficient Systems (iPower3Es) Lab at UC San Diego, led by Prof. Hanh-Phuc Le, focuses on research at the boundary between and deep into the two areas: integrated circuits and power electronics. The group’s goal is to create miniaturized/integrated circuit designs and power management systems that achieve optimal trade-offs among size, performance, and efficiency. Applications of interest include various electronic devices and systems from low power to high power, smartphones to data centers and telecommunication systems, battery-powered components to renewable- and grid-power devices, and from stationary systems to robots, automotive devices, and aircraft.
Hahn-Phuc Le’s Bio
Hanh-Phuc Le received his B.S. from Hanoi University of Science and Technology in Vietnam (2004), M.S. from KAIST, Korea (2006), and PhD from UC Berkeley (2013), all in Electrical Engineering. In 2012, he co-founded and served as the CTO at Lion Semiconductor until October 2015. The company is currently shipping millions of battery chargers and PMIC products to several World’s leading smartphone makers. He was with the University of Colorado Boulder from 2016 to 2019. In September 2019, he joined the Jacobs School of Engineering at UC San Diego as an assistant professor in the Department of Electrical and Computer Engineering. Previously, he also held R&D positions at Oracle, Intel, Rambus, JDA Tech in Korea, and the Vietnam Academy of Science and Technology (VAST) in Vietnam. He received the 2012-2013 IEEE Solid-State Circuits Society Pre-doctoral Achievement Award and the 2013 Sevin Rosen Funds Award for Innovation at UC Berkeley. He authored two book chapters, over 50 journal and conference papers including a COMPEL 2019 Best Paper Award, and is an inventor with 18 U.S. patents (10 granted and 8 pending). He serves as an associate editor of the IEEE Journal of Emerging and Selected Topics in Power Electronics (JESTPE), the TPC Chair/co-chair for the International Workshop on Power Supply On Chip (PwrSoC 2018, 2020). He is currently the Chair of the IEEE Power Electronics Society Technical Committee on Power Conversion Systems and Components (IEEE PELS TC2).
Dejan Markovic | Efficient Computation at Every Scale: Neural Implants to Wafer Scale Computers
Dejan Markovic | Efficient Computation at Every Scale: Neural Implants to Wafer Scale ComputersProject Abstract
Technology scaling is power-limited, so compute energy efficiency improvements have to come from chip and system architectures. Increasing application diversity also argues for a more flexible compute architectures, further emphasizing the need for energy-efficient design methods. This includes not just chips, but system solutions and dealing with miniaturization and techniques ranging from medical implants to wafer-scale computers, domains that about seven orders of magnitude apart in power consumption, and things in between.
Dejan Markovic’s Bio
Dejan Markovic received the Dipl.Ing. degree from the University of Belgrade, Serbia, in 1998 and the M.S. and PhD (thesis) degrees from the University of California, Berkeley, in 2000 and 2006, respectively, all in Electrical Engineering. In 2006, he joined the faculty of the Electrical Engineering Department at the University of California, Los Angeles as an Assistant Professor. His current research is focused on digital integrated circuits and architectures for parallel data processing in wireless communications and neuroscience, including optimization methods and supporting CAD flows. Dr. Marković was awarded the CalVIEW Fellow Award in 2001 and 2002 for excellence in teaching and mentoring of industry engineers through the UC Berkeley distance learning program. In 2004, he was a co-recipient of the Best Paper Award at the IEEE International Symposium on Quality Electronic Design. He received the 2007 David J. Sakrison Memorial Prize from the Department of EECS, UC Berkeley.
Taylor Barton | Power in the Air for Massive Communication
Taylor Barton | Power in the Air for Massive CommunicationProject Abstract
How do the large cell towers that make up our cellular network manage to transmit high data-rate signals efficiently? They don’t! Energy efficiency in communications applications is getting worse over time, tied to increasing demands for higher and higher data rates. Solving this design problem is very difficult because it combines three challenging areas: gigahertz-frequency design, high-performance requirements (linearity, bandwidth), and energy efficiency. In this talk, we will look at radio frequency (RF) power amplifier topologies that tackle these challenges, and analog techniques designed to replace the digital signal processing in today’s cellular systems. Along the way, I will introduce some techniques to beat the efficiency/linearity tradeoff that has been plaguing power amplifier designers since the invention of radio.
Taylor Barton’s Bio
Taylor Barton is an Assistant Professor in the Department of Electrical, Computer, and Energy Engineering at the University of Colorado Boulder, where she holds the Lockheed Martin Faculty Fellowship for outstanding junior faculty. Prior to joining CU Boulder in 2016, she was an Assistant Professor at The University of Texas at Dallas for two years, and a post-doctoral associate in the Microsystems Technology Laboratories at the Massachusetts Institute of Technology. Dr. Barton received the Sc.D from MIT for her research in energy-efficient power amplifiers for wireless communications, and also holds Sc.B., M.Eng., and E.E. degrees from MIT’s EECS department. She is a member of the IEEE Microwave Theory and Techniques Society, IEEE Young Professionals, IEEE Women in Engineering, and received the Goodwin Medal for conspicuously effective teaching at MIT and the Analog Devices Outstanding Student Designer Award in 2011. Prof. Barton has received the AFSOR YIP and NSF CAREER awards.
Achintya Madduri | Power Grid Resiliency and Security
Achintya Madduri | Power Grid Resiliency and SecurityProject Abstract
The power grid is going through a remarkable renaissance because of the increasing availability of distributed energy resources (DERs) and internet of things (IoT) devices. In order to use DERs effectively without destabilizing the grid, power systems operators need to gather more data from the growing number of DERs to gain visibility into their real-time behavior. Operators will also need to actively manage DERs to unlock the full potential of clean energy technologies. IoT devices will play a crucial role in enabling the observability and controllability of DERs. However, the potential of an observable and controllable “smart grid” comes with huge risks of catastrophic failure at the hands of malicious cyber-attackers or even sloppy IoT device design. This talk will discuss the promise and challenges facing engineers and regulators as they navigate to the power grid cleaner and more resilient future.
Achintya Madduri’s Bio
Achintya received a PhD in electrical engineering at the University of California, Berkeley, and a MS in applied ocean science from the Scripps Institute of Oceanography at UC San Diego. His dissertation research explored the creation of a smart and scalable solar microgrid in order to efficiently electrify rural unelectrified regions. For the last three years, he worked as a senior engineer at Amber Kinetics Inc., a flywheel-based energy storage company in Union City, California. Achintya received his BS in Mechanical Engineering from Rice University. Achintya is currently a Global Security Systems Analyst at Lawrence Livermore National Laboratory.