Free Floating-Point Madness: Adder

The fully-featured floating point adder compiled for the
smallest possible area

Contact: Justin Schauer (jschauer@hmc.edu)

Here are all the files and documentation related to the opensource adder created by Justin Schauer for summer engineering research at Harvey Mudd College under the supervision of Dr. David Harris, an engineering professor at Harvey Mudd College.

(Up to Free Floating-Point Madness)

Floating Point Adder Generator

UPDATED 5/13/02

The adder has now been well verified for any precision meaning you can choose any combination of significand and exponent widths and get a valid adder. See documentation for specifics on verification. Verification has still only been performed on model with all default values chosen in the generator.

This generator allows you to create an adder of any precision. It also has options on what features you want the adder to have (such as denormal support, rounding modes, etc.). This generator is still at a very early stage and as such may be buggy and virtually all outputs are untested. For entertainment purposes only at this stage.

The full floating point adder. This is the complete Verilog code for the adder. It is seperated into different files for each of the modules. The code is fully commented. Also in the zip is the constants file that is included in every module. The constants are set up for the adder to be in single precision mode, but the comments should be sufficient to allow you to change them as you please.
The documentation. This is the documentation for the adder and includes a brief overview, a description of the inputs and outputs and how the control fields work, a fairly detailed description of the entire process used to get the results, some brief information on what verification has been done, and finally the results of synthesis in the form of an Area vs. Timing graph. These are in PDF format so you need ADOBE ACROBAT VIEWER.
Spring 2002 Presentation. As part of my research, I gave this presentation at the end of the Spring semester. It contains background info, progress, and future work.
The synthesis scripts. These are the Synopsis Design Compiler scripts we used to compile the Verilog code, so you can see exactly what options we used.
Miscellaneous Verilog Files. These are various other Verilog files that were used for verification (TestFixture.v) and synthesis (SynTestbed.v and mux4.v).
Test case generation code. This is the program we used to generate the directed and random test cases that we tested the adder with. In its current state, it only generates single precision test cases, and MUST be run on an Intel Pentium Pro based processor (it may work on other x86 processors, but we are only sure that it works on Pentium Pro based CPUs). Please note that Pentium Pro based CPUs include the Pentium 2, Celeron, and Pentium III CPUs as well as Pentium Pros. Source code is also included.

Pentium, Pentium Pro, Pentium 2, Celeron, and Pentium III are registered trademarks of Intel.